1. Field of the Invention
The present invention relates to microprocessor systems and, more specifically, to a microprocessor system able to store information frequently used in the execution of an application program.
2. Discussion of the Related Art
Generally speaking, the operation speed of a microprocessor system suffers when data is read/written. A processor in the system must connect to a storage device storing information (e.g., data and commands) to execute an application program, and this involves read/write operations. These storage devices, such as a hard disk or DRAM (Dynamic Random Access Memory), operate relatively slowly as compared to the processor. To solve these problems, most microprocessor systems employ an additional cache memory, which is embodied by memory devices such as SRAM (Static Random Access Memory), having a relatively fast speed. In the cache memory, data and commands, which are used by processors most recently, are temporarily stored. Additionally, data and commands, predicted by processors to be needed in the near future, may be stored. As a result, it is possible to improve operation speed by shortening the time to access data necessary to execute an application program. Recently, for the purpose of improving performance of microprocessor systems, numerous cache memories together with processors have been integrated onto one chip.
FIG. 1 is a block diagram of a conventional microprocessor system employing a cache memory. As shown, the conventional microprocessor system includes a processor 100, a cache controller 104, a storage device 108 and a bus 106. The processor 100 controls the entire microprocessor system such as reading information through the bus 106 from the storage device 108 or from the cache memory 102. In addition, the processor 100 stores information in the storage device 108 and the cache memory 102. The cache memory 102 temporarily stores commands and data, executed and generated by the processor 100 and outputs the stored information according to a request of the processor 100. The cache controller 104 controls storing and accessing information from the cache memory 102 by managing address information for the information. The storage device 108 is embodied by a hard disk or mass storage DRAM, and stores information for executing an application program.
In this conventional microprocessor system, the processor 100 connects to the storage device 108 to read/write data and commands for the purpose of executing an application program. A command and data, which are used by the processor 100, are temporarily stored in the cache controller 104. Then, when the application program is executed by the processor 100, the processor 100 first attempts to retrieve the information from the cache controller 104. If necessary information exists in the cache memory 102, the cache controller 104 transfers the information stored in the cache memory 102 to the processor 100. However, if the information requested by the processor 100 does not exist in the cache memory 102, the processor 100 obtains the information by connecting to the storage device 108, and executed data is stored through the cache controller 104 in the cache memory 102.
Accordingly, in microprocessor systems based on a conventional cache, if a context switch occurs, it is essential to delete cache entries used in execution of the application program from the cache in order to execute a next application program. These operations are referred to as “flush & fill” operations. However, as a result of the flush & fill operation, an operation speed of the system becomes slow.